1. Field of the Invention
The present invention relates generally to a fin structure and a fin structure cutting process, and more specifically to a fin structure and a fin structure cutting process applying a bump beside a fin structure.
2. Description of the Prior Art
With increasing miniaturization of semiconductor devices, various multi-gate MOSFET devices have been developed. The multi-gate MOSFET is advantageous for the following reasons. First, manufacturing processes of multi-gate MOSFET devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the multi-gate MOSFET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased.
A multi-gate MOSFET has a gate formed on fin-shaped structures, and the fin-shaped structures are formed on a substrate, wherein the fin-shaped structures formed by etching the substrate are strip structures parallel to each other. With the demands of miniaturization of semiconductor devices, the width of each fin-shaped structure narrows and the spacings between the fin-shaped structures shrink. Thus, forming fin-shaped structures which can achieve the required demands under the restrictions of miniaturization, physical limitations and various processing parameters becomes an extreme challenge.
On the other hand, in the present semiconductor process, a localized oxidation isolation (LOCOS) or a shallow trench isolation (STI) are normally used to isolate each MOS. However, with the decrease in both design size and fabricating line width of the semiconductor wafer, the drawbacks of pits, crystal defects and longer bird's beak in the LOCOS process will greatly affect the characteristics of the semiconductor wafer. As well, the field oxide produced in the LOCOS process occupies a larger volume to affect the integration of the semiconductor wafer. Thus, in the submicron semiconductor process, the STI process is widely used as an isolation technique. The STI structure is generally disposed in a substrate between two adjacent MOS transistors and surrounds active areas of the substrate, to prevent carriers such as electrons or electrical holes from diffusing between the two adjacent MOS transistors through the substrate, which would lead to junction current leakage. Accordingly, the STI process can isolate components from each other and has advantages of smaller size, low cost and improved integration.
Multi-gate MOSFETs formed by integrating fin structures with isolation structures are widely used in the modern industry.